Multiplier having a reduced number of partial product calculations
US5119325A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1990 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Dec 4, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.