Semiconductor memory device having burn-in test function
US5119337A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1990 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Apr 16, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device such as dynamic random access memories comprises a work line drive circuit provided with two MOS transistors and a word line to which a word line drive signal is supplied, a substrate bias generation circuit for applying a bias voltage to a semiconductor substrate for MOS transistors, a burn-in mode detection circuit for detecting a burn-in test mode signal, and a substrate bias control circuit for controlling the substrate bias generation circuit. When the semiconductor memory device is subjected to a burn-in test, the power supply level Vcc is increased to raise the voltage of the word line drive signal as compared to that at a normal operation. Accordingly, a high level word line drive signal will be applied to cell transistors, thereby performing correct screening thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.