Memory circuit having an erasable programmable memory
US5119339A · kind A · utility
1Cited by
1References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 6, 1989 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Feb 6, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuit includes an (E)EPROM and a programming voltage generator. This generator has a charge pump, a programming voltage controller and an edge controller which limits the increase of the programming voltage per unit of time. In the memory circuit, the controllers are fed back to the charge pump in order to switch the charge pump on or off in dependence on the programming voltage variation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.