Method of and apparatus for geometric pattern inspection employing intelligent imaged-pattern shrinking, expanding and processing to identify predetermined features and tolerances
US5119434A · kind A · utility
19Cited by
7References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1990 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Dec 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pattern inspection technique and apparatus, suitable for wafer and printed circuit board and related applications, employing novel intelligent imaged-pattern shrinking and expanding architecture to identify permissible line widths, spacing and in surrounding material context, and to identify defects or errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.