Application of state silos for recovery from memory management exceptions
US5119483A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1988 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Jul 20, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99939
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information. A microsequencer issues a series of microinstructions for each specifier or operation having been decoded, and also issues …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.