Memory board selection method and apparatus
US5119486A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 1989 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Jan 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention comprises a combined hardware and software method and apparatus for determining the size of memory located on a memory card inserted in the slot of a memory backplane of a computer system. The method and apparatus also provides a means for selecting the memory card which contains a requested memory location. Each memory slot has associated therewith a multibit code which indicates the size of the memory installed in the associated slot. The code from each slot is hardwired to the system memory controller which, given the codes can, as part of its memory initialization route, scan these bits and decode them in order to determine the amount of memory installed in each slot of the memory backplane. Each slot is further provided with an X-bit starting address which uniquely defines the lowest address available from the board inserted in the associated slot. The starting address from each slot is compared with the leftmost X-bits of the currently requested memory address. If the leftmost X-bits of the currently requested memory address are greater than the X-bit starting address of a given slot yet less than the X-bit starting address of the succeeding slot, then it is kno…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.