Zero overhead self-timed iterative logic
US5121003A · kind A · utility
50Cited by
6References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 10, 1990 |
| Grant date | Jun 9, 1992 |
| Priority date | — |
| Expiry date | Oct 10, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0966
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
CMOS domino logic is normally used only in two phases: precharge and logic evaluation. The invention uses a third phase to store data, which allows domino logic gates to be cascaded and pipelined without intervening latches. The inputs to this system must have strictly monotonic transitions during the logic evaluation phase and the precharge signal must be active during only the precharge phase. Furthermore, the pipelined system can feed its output back to the input to form an iterative structure. Such a feedback pipeline is viewed as a "loop" or "ring" of logic which circulates data until the entire computation is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.