Registered logic macrocell with product term allocation and adjacent product term stealing
US5121006A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 1991 |
| Grant date | Jun 9, 1992 |
| Priority date | — |
| Expiry date | Apr 22, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A macrocell with product term allocation and adjacent product term stealing is disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms and the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. Because programmable configuration switches can direct individual input product terms to the register logic instead of the OR gate, the register logic can be used even when an adjacent macrocell steals the OR gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.