Balance and protection for stacked RF amplifiers
US5121084A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1990 |
| Grant date | Jun 9, 1992 |
| Priority date | — |
| Expiry date | Mar 29, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/42
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A balance circuit for an amplifier circuit having 2.sup.M amplifiers serially biased across a supply potential node and a common potential node, where M is an integer greater than 0, and having respective 2.sup.M -1 interstage bias nodes and voltages between the amplifiers which are driven by respective input drive signals provided by 2.sup.M -1 2-way power splitters. A voltage reference circuit provides as to each power splitter first and second reference potentials respectively associated therewith. A plurality of control circuits are associated with respective power splitters and interstage nodes. Each control circuit is responsive to the associated first and second reference potentials and the interstage bias node for controlling the signal levels of the first and second drive signals provided by the associated 2-way splitter as a function of the associated interstage bias potential relative to the first and second reference potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.