Clock signal generator for video signal capable of generating a stable clock signal
US5121206A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 1990 |
| Grant date | Jun 9, 1992 |
| Priority date | — |
| Expiry date | May 22, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2005/91314
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A clock signal generator circuit includes a synchronous signal separation circuit for separating a synchronous signal from an input video signal; a phase-locked loop (PLL) circuit for generating a clock signal in synchronism with the synchronous signal of the video signal supplied from the separation circuit; a switch provided between the separation circuit and PLL circuit for intercepting a supply of the synchronous signal of the video signal from the separation circuit to the PLL circuit during a predetermined period; and a control circuit for further separating a vertical synchronous signal from the synchronous signal separated by the separation circuit and controlling, in accordance with the vertical synchronous signal, the switch so as to intercept a supply of the synchronous signal from the separation circuit to the PLL circuit during the predetermined period, the predetermined period being a pulse generation period during which there are present at least an equalizing pulse and dubbing preventing signal in the video signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.