High speed bus with virtual memory data transfer capability using virtual address/data lines
US5121487A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 1989 |
| Grant date | Jun 9, 1992 |
| Priority date | — |
| Expiry date | Feb 21, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.