Method of making a high speed, high density semiconductor memory package with chip level repairability
US5122475A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1990 |
| Grant date | Jun 16, 1992 |
| Priority date | — |
| Expiry date | Dec 20, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging structure mounts integrated circuit chips in a nested, cavity-up configuration, so as to permit access to the modules for reworkability, but without the use of a separate printed circuit board for support and interconnect among the modules. Each monolithic integrated circuit module comprises a cavity-up leadless chip carrier which is affixed to its own dedicated thermally and electrically conductive mounting base, that effectively plugs into an underlying ground plane, heat sink support. The mounting base may comprise of a thin conductive plate having a cylindrical stem, through which the mounting base is retained within an aperture in the underlying support. The underlying support has a plurality of cylindrical stem engaging apertures distributed in a matrix configuration, so that the insertion of a plurality of chip carrier mounting bases into the apertures of the matrix causes the mounting bases to be aligned edgewise in a tight edge-to-edge array. Distributed along edge portions of a mounting base contact regions to which conductive traces from topside wirebond links on the chip extend. Interconnection between chip carriers may be accomplished by elastomeric connect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.