Integrated logic circuit with clock skew adjusters
US5122679A · kind A · utility
110Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1989 |
| Grant date | Jun 16, 1992 |
| Priority date | — |
| Expiry date | Oct 13, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an integrated logic curcuit, a plurality of clock skew adjustors generate clocks having coincident phases in reaponse to frequency information and phase information fed from a clock source. These clock source and clock adjustors are arranged so that their individual signal delays may be substantially equalized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.