Symmetrical Exclusive-Or gate, and modification thereof to provide an analog multiplier
US5122687A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 1990 |
| Grant date | Jun 16, 1992 |
| Priority date | — |
| Expiry date | Oct 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/212
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Exclusive-Or circuit has a symmetrical arrangement of components in order to provide an identical input impedance for both input signals and to provide identical switching and signal propagation times. The circuit includes input stages (EF.sub.1, EF.sub.2 ; EF.sub.3, EF.sub.4) for receiving first and second input signals (V.sub.E1 ; V.sub.E2) and emitter followers (EF.sub.5, EF.sub.6, EF.sub.7, EF.sub.8) connected to the input stages. A current switch stage (T.sub.11, T.sub.12, T.sub.13, T.sub.14) is driven by the input stage for the first input signal, and an identical current switch stage (T.sub.21, T.sub.22, T.sub.23, T.sub.24) is driven by the input stage for the second input signal. These current switch stages are connected by load resistors (R.sub.1, R.sub.1) to one pole of an operating voltage source (U.sub.B). Another current switch stage (T.sub.15, T.sub.16), is connected between a current source (I.sub.O /2) and the current switch stage (T.sub.11, T.sub.12, T.sub.13, T.sub.14) that is driven by the input stage for the first input signal, and another identical current switch stage (T.sub.25, T.sub.26) is connected between a further current source (I.sub.O 2) and the cur…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.