Arrangement and method for identifying and localizing faulty circuits of a memory module
US5123016A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1990 |
| Grant date | Jun 16, 1992 |
| Priority date | — |
| Expiry date | Feb 1, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The identification of a faulty memory cells of a memory module ensues with the assistance of a selt-test method for whose implementation a processor (TPZ) is co-integrated on the memory module. In test mode, the test processor generates test patterns for the memory cells of the memory under test, evaluates the result signals output by the memory cells as a result of the test patterns and stores the addresses of memory cells that were identified as being faulty. With the assistance of the addresses of the faulty memory cells, the test processor produces a repair plan on the basis whereof rows and clumns having faulty memory cells are replaced with the assistance of replacemnet rows and replacement columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.