Phase synchronization pull-in system in bit error detecting apparatus
US5123020A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1990 |
| Grant date | Jun 16, 1992 |
| Priority date | — |
| Expiry date | Mar 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase synchronization pull-in system used in a bit error detecting apparatus includes a monitored circuit for inputting an input signal and processing the input signal when an operation of the monitored circuit is to be monitored, a standard circuit for processing an output of the monitored circuit inversely to the processing in the monitored circuit, a phase synchronization circuit for inputting the input signal of the monitored circuit and adjusting a first delay time of the input signal so that the first delay time coincides with a second delay time of the output of the standard circuit corresponding to the input signal, a bit error detecting circuit for detecting a difference between the input signal, after being delayed through a variable delay circuit, and the output of the standard circuit, bit by bit, and a controller for controlling the adjusting of the first delay time, a monitoring operation, and a phase synchronization pull-in operation. In the phase synchronization pull-in operation, the first delay time is obtained in the phase synchronization circuit based on whether or not a bit error rate measured by setting the delay time is higher than a predetermined value. Th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.