Integrated scalar and vector processors with vector addressing by the scalar processor
US5123095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1989 |
| Grant date | Jun 16, 1992 |
| Priority date | — |
| Expiry date | Jan 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.