Data processing system having four phase clocks generated separately on each processor chip
US5124571A · kind A · utility
25Cited by
7References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1991 |
| Grant date | Jun 23, 1992 |
| Priority date | — |
| Expiry date | Mar 29, 2011 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02B2075/027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital system generates a single-phase master clock and distributes it to multiple cards and chips incorporating the functional logic of the system. A circuit in each chip divides the single clock into four spaced clock phases at the same frequency as the master clock. The individual phases are then distributed to functional logic circuits within the same chip. The circuit generates the phases by detecting the midpoints of a triangular wave produced from the single-phase master clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.