Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor
US5124589A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1991 |
| Grant date | Jun 23, 1992 |
| Priority date | — |
| Expiry date | Apr 25, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.