Digital push-pull driver circuit
US5126588A · kind A · utility
21Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1990 |
| Grant date | Jun 30, 1992 |
| Priority date | — |
| Expiry date | Jan 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital push-pull driver circuit comprising two output transistors which are alternatingly controlled into the conducting state by a data control circuit and to whose common connection point a load to be driven is connected. One slope steepness reducing, enable-dependent delay circuit each is connected between the control electrode of each of the two output transistors and the data control circuit. The output of each delay circuit is connected to an enable input of the respective other delay circuit. The delay times of the two delay members are at least as long as the width of the steepness-reduced pulse slopes in terms of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.