Josephson integrated circuit having an output interface capable of providing output data with reduced clock rate
US5126598A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1990 |
| Grant date | Jun 30, 1992 |
| Priority date | — |
| Expiry date | Sep 28, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S505/859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Josephson integrated circuit includes a Josephson logic processor operated at a first clock rate, and a latch circuit formed of Josephson devices operated at the first clock rate for receiving output data from the Josephson processor together with a status signal for holding the output data. The latch circuit is supplied with a clear signal for resetting the output data therefrom. In addition, the invention includes therefrom a data output circuit formed of Josephson devices operated in response to a second clock rate that is slower than the first clock rate, wherein the data output circuit has an output terminal and supplied with the output data held in the latch means for passing the output data to the output terminal at the second clock rate. Further, the data output means produces the clear signal at the second clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.