Integrated cache SRAM memory having synchronous write and burst read
US5126975A · kind A · utility
102Cited by
1References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 24, 1990 |
| Grant date | Jun 30, 1992 |
| Priority date | — |
| Expiry date | Oct 24, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated cache memory device using SRAM cells is disclosed. The integrated cache memory has synchronized write capability and burst read capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.