Computer look-ahead instruction issue control
US5127093A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 1989 |
| Grant date | Jun 30, 1992 |
| Priority date | — |
| Expiry date | Jan 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for scheduling instruction issuance in a vector register computer achieves increased efficiency of operation by performing pre-issuance checks to determine if resources requested by the instruction will be available when the instruction issues. A decoding apparatus first determines particular resources requested by the instruction, which includes apparatus for decoding vector register requests, functional unit requests, and address and scalar register path requests. Following decoding, a conflict resolution apparatus checks resource reservation flags to determine if the requested resources will be available when the instruction issues. If any requested resources will be busy, the system issues a primary conflict signal. At the scheduled instruction issuance time, the system again checks the resource reservation flags in response to the primary conflict signal. If the requested resources are still busy, the system generates a secondary conflict signal for as long as the requested resources remain busy. Finally, when the instruction issues, the system sets the resource reservation flags to reserve the requested resources for the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.