High charge capacity focal plane array readout cell
US5128534A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1990 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | Jul 17, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/33
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A high charge capacity readout cell in a hybrid focal plane detector array on a complementary metal oxide semiconductor integrated circuit chip. An input transistor that provides a buffer for the detectors of the array, couples to a source of bias voltage, which controls the operation of the transistor. An integrating capacitor uses a variable source of terminating voltage to increase the amount of charge it integrates. A read signal causes an output transistor to read the charge from the capacitor to a readout line and to initialize the capacitor. The termination voltage of the integrating capacitor is changed during the time that the detector current is integrated, thus increasing the change in total voltage across the capacitor. This allows a greater amount of charge to be integrated with the capacitor which improves the signal-to-noise ratio of the focal plane array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.