Output circuit of semiconductor integrated circuit with reduced power source line noise
US5128567A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1989 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | May 1, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output circuit of a semiconductor integrated circuit includes a plurality of output transistors having different current driving abilities for a load, and a plurality of signal delay means for delaying signals for driving each of the output transistors by different delay times, wherein the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a first delay time is set to be larger than the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a second delay time shorter than the first delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.