Apparatus and method for providing notification of bit-cell failure in a redundant-bit-cell memory
US5128944A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1991 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | Jan 11, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable, programmable ROM (10) with three redundant bit-cell arrays (10A, 10B, 10C) includes an error-flagging circuit (30) that detects bit-cell failures and provides notification of each such failure. The error-flagging circuit (30) includes a plurality of XOR gates (32), each receiving the corresponding redundant data bits for one of the bits of an addressed byte, and a NOR gate (36) which receives the outputs from each of the XOR gates (32). Each XOR gate detects when the logic states for the input redundant bits are not identical, indicating a bit-cell failure has occurred, and provides a corresponding logic state output. The NOR gate (36) detects when any of the XOR gates (32) has indicated a bit-cell failure, and generates an error-flag output providing notification of such failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.