High speed image processing computer
US5129060A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1989 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | Jan 24, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). Mask da…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.