System for minimizing initiator processor interrupts by protocol controller in a computer bus system
US5129072A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1989 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | Mar 8, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system employing a common bus that is shared by an initiator and a plurality of targets, there is provided a method and apparatus that prevents data stored in a buffer, when one of the targets temporarily suspends a data transfer with the initiator, from being overwritten, while simultaneously minimizing the number of interrupts that must be employed to effect the data transfer. According to the disclosed invention, the initiator is interrupted by a second target only after the transfer of data from the initiator to a first target has been temporarily suspended, and only after the second target has reselected the bus. After the second target has reselected the bus, data read from the second target and transferred to the initiator is stored in a synchronous stack in the initiator to prevent any data remaining in the buffer from being overwritten. Data stored in the buffer is then stored in a predetermined location, such as RAM, in the initiator so that the data stored in the synchronous stack can be transferred to the buffer without loss of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.