Distributed interlock apparatus and distributed interlock management method
US5129089A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 1991 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | Oct 3, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interlocking of addresses in a system with parallel processors using a common memory space is managed by maintaining for each processor a record of the lock state of the system. When a processor seeks to initiate a transaction, the transaction is analyzed against the lock state record, and the processor's request for access to an intercommunication bus is transmitted only when the lock state of the system is in condition to process the transaction. By monitoring and analyzing bus transactions, the lock state record of each processor is maintained up to date. By thus blocking a transaction involving a locked address before the bus is requested, the tying up of the bus in futile activity is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.