Phase-locking circuit for swept synthesized source preferably having stability enhancement circuit
US5130670A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1991 |
| Grant date | Jul 14, 1992 |
| Priority date | — |
| Expiry date | Aug 1, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03C3/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-lock loop for a swept synthesized source in which hysteresis, tuning nonlinearity, and drift over time and temperature of an oscillator incorporated into the swept synthesized source are compensated. The tuning current to the oscillator is initialized to zero to eliminate hysteresis effects. Then, the pretune current is set to produce the minimum operating frequency of the oscillator. Next, the main phase-lock loop is closed, and a low-frequency synthesizer is swept to in turn sweep the oscillator over a selected frequency span. If the selected frequency span extends over other frequency bands, the oscillator is swept to the maximum frequency of the present band and held at this frequency by a track and hold circuit. The main phase-lock loop is opened, the low-frequency synthesizer is re-initialized, the main phase-lock loop is again closed, and the low-frequency synthesizer is swept again. Each frequency band is crossed in a similar manner until the selected frequency span is swept. In order to improve phase-noise and transient response performance of the low-frequency synthesizer, a phase-lock loop speed-up and stability enhancement circuit comprising a zener diode connec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.