Graphics frame buffer with RGB pixel cache
US5131080A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1990 |
| Grant date | Jul 14, 1992 |
| Priority date | — |
| Expiry date | Dec 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/127
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A graphics system uses a programmable tile size shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM's. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. Tiles are cached. Tiles for RGB pixel are cached in an RGB cache, while Z values are cached in a separate cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.