System having a host independent input/output processor for controlling data transfer between a memory and a plurality of I/O controllers
US5131081A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1989 |
| Grant date | Jul 14, 1992 |
| Priority date | — |
| Expiry date | Mar 23, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main processing unit and the I/O controllers. The I/O processor includes an internal memory for storing information pertinent to data transfer from each I/O channel including the address where channel programs, decision tables and data buffers are maintained in external memory. A sequencer executes a specialized instruction set which includes instructions that invoke an interpretation means enabling examination of status registers of the I/O controllers and/or data values therefrom and the branching of execution based thereon. The I/O processor and I/O controllers may be interconnected with a local external memory via a local bus which is selectively coupled with a system bus interconnecting the main processor unit and main external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.