LSI gate array having reduced switching noise
US5132563A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1991 |
| Grant date | Jul 21, 1992 |
| Priority date | — |
| Expiry date | Aug 14, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
As the number of output circuits in LSI or VLSI circuits increases, the chance of many large output circuits operating as a same instant increases, which can cause a malfunction in the logic due to induced switching noise. In order to prevent such a problem, the switching speed of the driving buffer circuit for an output buffer circuit is controlled. By reducing the switching capacity of the driving circuit, the switching speed of the total circuit is not greatly affected and the noise is greatly decreased. Control of the switching capacity of the driving buffer circuit is performed by master slice technology. This opposite design concept, compared to that of prior art LSI design, has been proved by experiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.