Horizontal synchronizing signal separation circuit for a display apparatus
US5132794A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1991 |
| Grant date | Jul 21, 1992 |
| Priority date | — |
| Expiry date | Jun 11, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The horizontal synchronizing signal separation circuit extracts pulses indicative of horizontal synchronizing timing from a composite synchronizing signal which includes a horizontal synchronizing signal and a vertical synchronizing signal. When detecting the rising edge of the composite synchronizing signal, a rising edge detection circuit generates a pulse signal. A counter counts the number of the pulses in a clock signal. The output of the counter is supplied to a decoder which decodes the output of the counter and outputs timing signals. Using the timing signals, a control signal is generated to control a gate to which the output of the rising edge detection circuit is supplied. The output of the gate is used for generating a separated horizontal synchronizing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.