High speed digital computing system
US5132921A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1989 |
| Grant date | Jul 21, 1992 |
| Priority date | — |
| Expiry date | Nov 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connected to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the next higher order stage of the second full adder, and the fourth source is connected to the augend input of the second full adder. The full adders are implemented with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipation at high data processing speeds. The circuitry is physically laid out on an …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.