Method and apparatus for designing integrated circuits for testability
US5132974A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 1989 |
| Grant date | Jul 21, 1992 |
| Priority date | — |
| Expiry date | Oct 24, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is a method for designing testability into an integrated circuit. This method is termed register transfer scan (RTS). The RTS method comprises two primary rules. The first rule is that every global feedback path in the functional circuit must contain at least one scannable storage element, i.e. it must be accessible such that data can be placed into it or read from it without passing the data through the functional circuitry of the chip. The second rule of the RTS method is that the controls for those storage elements that are not scannable are held inactive when data is being scanned into or out of the scannable storage elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.