Synchronous counter terminal count output circuit
US5134315A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 1991 |
| Grant date | Jul 28, 1992 |
| Priority date | — |
| Expiry date | Feb 7, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00353
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronous counter flip flop circuit (20) incorporates a logical AND input circuit (22) having multiple inputs (24) and a first output (25) delivering a first count signal upon concurrence of count logic signals at count logic signal inputs (BIT0-BIT7) with a count enable clock signal at a count enable clock signal input (CET). A count delay circuit (30) is coupled to the first output (25) to provide a second output (32) in parallel with the first output (25) for delivering a delayed second count signal. A logical AND intermediate circuit coupling (34) having first and second inputs coupled respectively to the first and second outputs (25,32) provides a third output (35) delivering a third count signal which is a filtered intermediate terminal count signal (TC). An inverting output buffer circuit (26) provides a final inverted filtered terminal count signal (TC) at the final terminal count output (28). The delay circuit (30) is constructed to provide a selected delay time interval longer than the transient duration time interval of decoding noise spikes for filtering out the decoding noise spikes at the logical AND intermediate circuit coupling (34).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.