Synchronization circuit for a synchronous switching system
US5134636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1991 |
| Grant date | Jul 28, 1992 |
| Priority date | — |
| Expiry date | Feb 20, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0629
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The synchronization circuit resynchronizes the data bits received from remote devices on line or link (20-1) with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in an n-bit cyclic buffer (114-1) with the received bit clock CS. The arranged bits are sequentially picked at the opposite buffer position with the central clock CO. The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.