Test apparatus performing runtime replacement of program instructions with breakpoint instructions for processor having multiple instruction fetch capabilities
US5134701A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1989 |
| Grant date | Jul 28, 1992 |
| Priority date | — |
| Expiry date | Feb 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The test apparatus for monitoring the operation of a processor that has multiple instruction fetch capability monitors the instruction memory to record the sequence of program instructions that are retrieved by the processor from program memory. The test apparatus determines when a jump operation is executed and determines the target of the jump oepration by inserting a break point instruction in place of one of the two program instructions that is retrieved by the processor from program memory. This instruction substitution is accomplished by an instruction jamming circuit that forces the break point instruction onto the processor data bus as part of the program instruction fetch cycle in lieu of one of the instruction retrieved as part of the execution of the jump instruction. If the break point operation is executed, then the target address of the jump operation is the address location that contains the break point instruction that was substituted for one of the program instructions retrieved from the instruction memory. In this case, the test apparatus responds to the execution of the break point instruction by replacing the program instruction originally retrieved from program…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.