Bus interface interrupt apparatus
US5134706A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1990 |
| Grant date | Jul 28, 1992 |
| Priority date | — |
| Expiry date | Apr 19, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface interrupt arrangement is disclosed which provides separate interrupt controllers for each bus in a multibus computer system where the processor is connected to one of the busses. Interrupt requests decided on each of the busses other than a primary bus to which the processor is connected are input along with interrupts from circuits connected to the primary bus to the interrupt controller for the primary bus. The interrupt request decided by the interrupt controller for the primary bus is connected to an interrupt input of the processor. All interrupt controllers are connected to the primary bus and may be accessed by the processor. When an interrupt from one of the busses other than the primary bus is chosen by the processor, the processor must read the interrupt controllers to determine first what bus, and then identify the circuit that generated the interrupt that has been acknowledged. Using this information circuits in the bus interface interrupt arrangement are operated to pass data and addresses between the primary bus and the chosen bus. These circuits are operated in a manner to pass data between busses having different data path sizes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.