BiCMOS input circuit for detecting signals out of ECL range
US5136189A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 1990 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | Apr 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A BiCMOS input circuit which is capable of detecting signals below a particular range, such as ECL signals, is presented. The circuit is useful in conserving the number of pins in a BiCMOS integrated circuit in that a signal below normal ECL levels can trigger special functions, such as testing. The circuit has a plurality of CMOS inverter circuits connected in series with the input node of the first inverter connected to the input terminal of the circuit and the output node of the last inverter circuit connected to the output terminal of the circuit. Diode-connected bipolar transistor created a potential difference between V.sub.CC and the source electrode of PMOS transistor of each CMOS inverter circuit in a declining fashion from the first inverter to the last inverter. The last inverter circuit has no potential difference at all so that its output has a full CMOS swing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.