Interconnecting layer on a semiconductor substrate
US5136355A · kind A · utility
4Cited by
7References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1991 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | Mar 6, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor arrangement includes a substrate having a plurality of transistors formed therein and a tungsten layer thereon in the form of elongate tracks serving to interconnect the transistors. Localized regions of highly doped semiconductor material underlie the tracks and form an ohmic contact therewith. The tungsten layer is overlaid with an electrically insulating oxide on which further electrical interconnections are present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.