Hardware interface to a high-speed multiplexed link
US5136584A · kind A · utility
156Cited by
11References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 11, 1990 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | Jul 11, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5672
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.