Digital signal multiplexing apparatus and demultiplexing apparatus
US5136587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1990 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | Sep 7, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0089
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital signal multiplexing apparatus has n (n is an arbitrary integer) multiplexing circuits (11-1n) for converting input signals from a plurality of lines into m (m is an arbitrary integer) parallel signals which are added with added bits and have a first transmission speed. A parallel-serial conversion circuit (40) converts the m parallel signals from the n multiplexing circuits into a serial multiplexed signal by a parallel-serial conversion. A bus (30) connects the n multiplexing circuits and the parallel-serial conversion circuit. The n multiplexing circuits respectively have a circuit for successively transmitting the m parallel signals to the bus using a pluse signal having a second transmission speed which is n times the first transmission speed. A digital signal demultiplexing circuit has a serial-parallel conversion circuit (75) for converting a serial input signal into m (m is an arbitrary integer) parallel signals having a predetermined transmission speed. N (n is an arbitrary integer) demultiplexing circuits (51-5n) demultiplexes added bits from the m parallel signals from the serial-parallel conversion circuit (75) and outputs the added bits on a plurality of lines…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.