Interleaving method and apparatus
US5136588A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 1989 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | Nov 14, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2703
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaving method and apparatus suitable for burst error correction occurring in data transmission or reading of recording medium. In the interleaving method in which data to be transmitted is once written in a storing means and then read to be output in order different from a writing order, a plurality of counters for dividingly generating addresses of the storing means is used; and an operational relationship between the counters is changed between writing and reading of the storing means. ROMs for address translation can be omitted so that the number of gates is reduced very much. Thus, a reasonable interleaving apparatus suitable for LSI formation can be realized. In addition, since ROMs for address translation interposed between the counter and the storing means in the conventional apparatus are omitted, access time for the storing means can be shortened substantially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.