Method and apparatus for providing bus parity
US5136594A · kind A · utility
4Cited by
8References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 14, 1990 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | Jun 14, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for checking parity on, for example, an Extended Industry Standard Architecture (EISA) bus. In a 32-bit information bus, four parity pins may be provided. During a first clock cycle the pins are all driven high and during a second clock cycle the pins are all driven low. This characteristic pattern is detected by a slave device and provides an indication that parity data will be transmitted on the four parity pins. After an indication of parity support the pins are provided with parity bits for error detection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.