Microprocessor operable in a functional redundancy monitor mode
US5136595A · kind A · utility
27Cited by
6References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 24, 1989 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | May 24, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor system having a functional redundancy monitor operation mode. This processor system includes two processors, one processor to receive external signals from a monitored processor, and compare the external signals with signals generated internally every bus cycle. The monitoring processor then produces a comparison resultant signal, indicating if a match occurs. The processor further includes a timer circuit for defining a period during which the comparison resultant signal is output. After that period, the comparison result signal is set to a logic level representative of a misoperation of the processor monitored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.