Apparatus and method for reducing interference in two-level cache memories
US5136700A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1989 |
| Grant date | Aug 4, 1992 |
| Priority date | — |
| Expiry date | Dec 22, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor computer system, a number of processors are coupled to main memory by a shared memory bus, and one or more of the processors have a two level direct mapped cache memory. When any one processor updates data in a shared portion of the address space, a cache check request signal is transmitted on the shared data bus, which enables all the cache memories to update their contents if necessary. Since both caches are direct mapped, each line of data stored in the first cache is also stored in one of the blocks in the second cache. Each cache has control logic for determining when a specified address location is stored in one of its lines or blocks. To avoid spurious accesses to the first level cache when a cache check is performed, the second cache has a special table which stores a pointer for each line in said first cache array. This pointer denotes the block in the second cache which stores the same data as is stored in the corresponding line of the first cache. When the control logic of the second cache indicates that the specified address for a cache check is located in the second cache, a lookup circuit compares the pointer in the special table which corresponds …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.