Controlled slew rate buffer
US5138194A · kind A · utility
39Cited by
8References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1990 |
| Grant date | Aug 11, 1992 |
| Priority date | — |
| Expiry date | Nov 8, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A controlled slew rate buffer is disclosed which comprises a driver receiving voltage along a voltage supply line and includes feedback apparatus which senses the noise level along the voltage supply line and slows the speed of the buffer when the noise level passes a given threshold. The driver comprises at least one of (1) first and second VSS voltage sources and (2) first and second VDD voltage sources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.