Blocking message transmission or signaling error in response to message addresses in a computer interconnect coupler for clusters of data processing devices
US5138611A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1991 |
| Grant date | Aug 11, 1992 |
| Priority date | — |
| Expiry date | Aug 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer interconnect coupler has channel transmitters and channel receivers and logic circuitry for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgment responsive to the incoming message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added. The coupler also includes a plurality of timers which determine fau…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.